발간년도 : [2016]
| 논문정보 |
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| 논문명(한글) |
[Vol.11, No.4] Efficient Implementation of Hybrid Normal Basis Multiplier over GF(2m) |
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| 논문투고자 |
Yong-Suk Cho, Kyoung-Il Min |
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| 논문내용 |
Efficient hardware implementations of arithmetic operations in the Galois field GF(2m) are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing multiplication are highly required. Hardware implementations of finite field arithmetic using normal basis are advantageous due to the fact that the squaring operation can be done at almost no cost. In this paper, efficient implementation of hybrid multiplier using normal basis in GF(2m) is presented. The hybrid multiplier is of sequential type, i.e., after receiving the coordinates of the two input field elements, they go through d, 1≤d≤m, iterations (i.e., clock cycles) to finally yield all the coordinates of the product in parallel. The value of d can be arbitrarily selected by the designer to set the trade-off between area and speed. The proposed multiplier architecture is faster than bit-serial architectures but with lower area complexity than bit-parallel ones, The most significant feature of the proposed architecture is that a trade-off between hardware complexity and delay time can be achieved. This makes the proposed multipliers suitable for applications where the value of m is large but space is of concern, e.g., resource constrained cryptographic systems. |
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